2011-02-01 Dave Tapuska <dtapuska@rim.com>

        Reviewed by Gavin Barraclough.

        MacroAssemblerARM would generate code that did 32bit loads
        on addresses that were not aligned. More specifically it would
        generate a ldr r8,[r1, #7] which isn't valid on ARMv5 and lower.
        The intended instruction really is ldrb r8,[r1, #7]; ensure we
        call load8 instead of load32.

        https://bugs.webkit.org/show_bug.cgi?id=46095

        * assembler/MacroAssemblerARM.h:
        (JSC::MacroAssemblerARM::set32Test32):
        (JSC::MacroAssemblerARM::set32Test8):

git-svn-id: http://svn.webkit.org/repository/webkit/trunk@77248 268f45cc-cd09-0410-ab3c-d52691b4dbfc
parent 2659d72e
2011-02-01 Dave Tapuska <dtapuska@rim.com>
Reviewed by Gavin Barraclough.
MacroAssemblerARM would generate code that did 32bit loads
on addresses that were not aligned. More specifically it would
generate a ldr r8,[r1, #7] which isn't valid on ARMv5 and lower.
The intended instruction really is ldrb r8,[r1, #7]; ensure we
call load8 instead of load32.
https://bugs.webkit.org/show_bug.cgi?id=46095
* assembler/MacroAssemblerARM.h:
(JSC::MacroAssemblerARM::set32Test32):
(JSC::MacroAssemblerARM::set32Test8):
2011-02-01 Darin Fisher <darin@chromium.org>
Reviewed by Eric Seidel.
......
......@@ -661,21 +661,26 @@ public:
set32Compare32(cond, left, right, dest);
}
void set32Test32(Condition cond, Address address, Imm32 mask, RegisterID dest)
void set32Test32(Condition cond, RegisterID reg, Imm32 mask, RegisterID dest)
{
load32(address, ARMRegisters::S1);
if (mask.m_value == -1)
m_assembler.cmp_r(0, ARMRegisters::S1);
m_assembler.cmp_r(0, reg);
else
m_assembler.tst_r(ARMRegisters::S1, m_assembler.getImm(mask.m_value, ARMRegisters::S0));
m_assembler.tst_r(reg, m_assembler.getImm(mask.m_value, ARMRegisters::S0));
m_assembler.mov_r(dest, ARMAssembler::getOp2(0));
m_assembler.mov_r(dest, ARMAssembler::getOp2(1), ARMCondition(cond));
}
void set32Test32(Condition cond, Address address, Imm32 mask, RegisterID dest)
{
load32(address, ARMRegisters::S1);
set32Test32(cond, ARMRegisters::S1, mask, dest);
}
void set32Test8(Condition cond, Address address, Imm32 mask, RegisterID dest)
{
// ARM doesn't have byte registers
set32Test32(cond, address, mask, dest);
load8(address, ARMRegisters::S1);
set32Test32(cond, ARMRegisters::S1, mask, dest);
}
void add32(Imm32 imm, RegisterID src, RegisterID dest)
......
Markdown is supported
0% or .
You are about to add 0 people to the discussion. Proceed with caution.
Finish editing this message first!
Please register or to comment