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  • msaboff@apple.com's avatar
    JSC: There should be a disassembler for ARM Thumb 2 · ac9f0e52
    msaboff@apple.com authored 
    https://bugs.webkit.org/show_bug.cgi?id=115827

Reviewed by Filip Pizlo.

Source/JavaScriptCore: 

Added a new disassembler for ARMv7 Thumb2 instructions for use by the JSC debugging
and profiling code.  The opcode coverage is currently not complete.  It covers all
of the integer instructions JSC currently emits, but only a limited number of
floating point opcodes.  Currently that is just the 64 bit vmov and vmsr instructions.

The disassembler is structured as a base opcode class ARMv7DOpcode with sub-classes
for each instruction group.  There is a public format method that does the bulk of
the disassembly work.  There are two broad sub-classes, ARMv7D16BitOpcode and
ARMv7D32BitOpcode, for the 16 bit and 32 bit opcodes.  There are sub-classes under
those two classes for individual and related groups of opcodes.  Instructions are
"dispatched" to the right subclass via two arrays of linked lists in the inner classes
OpcodeGroup.  There is one such inner class for each ARMv7D16BitOpcode and ARMv7D32BitOpcode.
Each OpcodeGroup has a mask and a pattern that it applies to the instruction to determine
that it matches a particular group.  OpcodeGroup uses a static method to reinterpret_cast
the Opcode object to the right base class for the instruction group for formatting.
The cast eliminates the need of allocating an object for each decoded instruction.
Unknown instructions are formatted as ".word 1234" or ".long 12345678" depending whether
the instruction is 16 or 32 bit.

* JavaScriptCore.xcodeproj/project.pbxproj:
* disassembler/ARMv7: Added.
* disassembler/ARMv7/ARMv7DOpcode.cpp: Added.
(ARMv7Disassembler):
(OpcodeGroupInitializer):
(JSC::ARMv7Disassembler::ARMv7DOpcode::init):
(JSC::ARMv7Disassembler::ARMv7DOpcode::startITBlock):
(JSC::ARMv7Disassembler::ARMv7DOpcode::saveITConditionAt):
(JSC::ARMv7Disassembler::ARMv7DOpcode::fetchOpcode):
(JSC::ARMv7Disassembler::ARMv7DOpcode::disassemble):
(JSC::ARMv7Disassembler::ARMv7DOpcode::bufferPrintf):
(JSC::ARMv7Disassembler::ARMv7DOpcode::appendInstructionName):
(JSC::ARMv7Disassembler::ARMv7DOpcode::appendRegisterName):
(JSC::ARMv7Disassembler::ARMv7DOpcode::appendRegisterList):
(JSC::ARMv7Disassembler::ARMv7DOpcode::appendFPRegisterName):
(JSC::ARMv7Disassembler::ARMv7D16BitOpcode::init):
(JSC::ARMv7Disassembler::ARMv7D16BitOpcode::doDisassemble):
(JSC::ARMv7Disassembler::ARMv7D16BitOpcode::defaultFormat):
(JSC::ARMv7Disassembler::ARMv7DOpcodeAddRegisterT2::format):
(JSC::ARMv7Disassembler::ARMv7DOpcodeAddSPPlusImmediate::format):
(JSC::ARMv7Disassembler::ARMv7DOpcodeAddSubtractT1::format):
(JSC::ARMv7Disassembler::ARMv7DOpcodeAddSubtractImmediate3::format):
(JSC::ARMv7Disassembler::ARMv7DOpcodeAddSubtractImmediate8::format):
(JSC::ARMv7Disassembler::ARMv7DOpcodeBranchConditionalT1::format):
(JSC::ARMv7Disassembler::ARMv7DOpcodeBranchExchangeT1::format):
(JSC::ARMv7Disassembler::ARMv7DOpcodeBranchT2::format):
(JSC::ARMv7Disassembler::ARMv7DOpcodeCompareImmediateT1::format):
(JSC::ARMv7Disassembler::ARMv7DOpcodeCompareRegisterT1::format):
(JSC::ARMv7Disassembler::ARMv7DOpcodeCompareRegisterT2::format):
(JSC::ARMv7Disassembler::ARMv7DOpcodeDataProcessingRegisterT1::format):
(JSC::ARMv7Disassembler::ARMv7DOpcodeGeneratePCRelativeAddress::format):
(JSC::ARMv7Disassembler::ARMv7DOpcodeLoadFromLiteralPool::format):
(JSC::ARMv7Disassembler::ARMv7DOpcodeLoadStoreRegisterImmediate::format):
(JSC::ARMv7Disassembler::ARMv7DOpcodeLoadStoreRegisterOffsetT1::format):
(JSC::ARMv7Disassembler::ARMv7DOpcodeLoadStoreRegisterSPRelative::format):
(JSC::ARMv7Disassembler::ARMv7DOpcodeLogicalImmediateT1::format):
(JSC::ARMv7Disassembler::ARMv7DOpcodeMiscAddSubSP::format):
(JSC::ARMv7Disassembler::ARMv7DOpcodeMiscBreakpointT1::format):
(JSC::ARMv7Disassembler::ARMv7DOpcodeMiscByteHalfwordOps::format):
(JSC::ARMv7Disassembler::ARMv7DOpcodeMiscCompareAndBranch::format):
(JSC::ARMv7Disassembler::ARMv7DOpcodeMiscHint16::format):
(JSC::ARMv7Disassembler::ARMv7DOpcodeMiscIfThenT1::format):
(JSC::ARMv7Disassembler::ARMv7DOpcodeMiscPushPop::format):
(JSC::ARMv7Disassembler::ARMv7DOpcodeMoveImmediateT1::format):
(JSC::ARMv7Disassembler::ARMv7DOpcodeMoveRegisterT1::format):
(JSC::ARMv7Disassembler::ARMv7D32BitOpcode::init):
(JSC::ARMv7Disassembler::ARMv7D32BitOpcode::doDisassemble):
(JSC::ARMv7Disassembler::ARMv7D32BitOpcode::defaultFormat):
(JSC::ARMv7Disassembler::ARMv7DOpcodeConditionalBranchT3::format):
(JSC::ARMv7Disassembler::ARMv7DOpcodeBranchOrBranchLink::format):
(JSC::ARMv7Disassembler::ARMv7DOpcodeDataProcessingModifiedImmediate::appendModifiedImmediate):
(JSC::ARMv7Disassembler::ARMv7DOpcodeDataProcessingModifiedImmediate::format):
(JSC::ARMv7Disassembler::ARMv7DOpcodeDataProcessingShiftedReg::appendImmShift):
(JSC::ARMv7Disassembler::ARMv7DOpcodeDataProcessingShiftedReg::format):
(JSC::ARMv7Disassembler::ARMv7DOpcodeFPTransfer::format):
(JSC::ARMv7Disassembler::ARMv7DOpcodeFPTransfer::appendFPRegister):
(JSC::ARMv7Disassembler::ARMv7DOpcodeDataProcessingRegShift::format):
(JSC::ARMv7Disassembler::ARMv7DOpcodeDataProcessingRegExtend::format):
(JSC::ARMv7Disassembler::ARMv7DOpcodeDataProcessingRegParallel::format):
(JSC::ARMv7Disassembler::ARMv7DOpcodeDataProcessingRegMisc::format):
(JSC::ARMv7Disassembler::ARMv7DOpcodeHint32::format):
(JSC::ARMv7Disassembler::ARMv7DOpcodeLoadRegister::format):
(JSC::ARMv7Disassembler::ARMv7DOpcodeLoadSignedImmediate::format):
(JSC::ARMv7Disassembler::ARMv7DOpcodeLoadUnsignedImmediate::format):
(JSC::ARMv7Disassembler::ARMv7DOpcodeLongMultipleDivide::format):
(JSC::ARMv7Disassembler::ARMv7DOpcodeUnmodifiedImmediate::format):
(JSC::ARMv7Disassembler::ARMv7DOpcodeDataPushPopSingle::format):
(JSC::ARMv7Disassembler::ARMv7DOpcodeStoreSingleImmediate12::format):
(JSC::ARMv7Disassembler::ARMv7DOpcodeStoreSingleImmediate8::format):
(JSC::ARMv7Disassembler::ARMv7DOpcodeStoreSingleRegister::format):
(JSC::ARMv7Disassembler::ARMv7DOpcodeVMOVDoublePrecision::format):
(JSC::ARMv7Disassembler::ARMv7DOpcodeVMOVSinglePrecision::format):
(JSC::ARMv7Disassembler::ARMv7DOpcodeVMSR::format):
* disassembler/ARMv7/ARMv7DOpcode.h: Added.
(ARMv7Disassembler):
(ARMv7DOpcode):
(JSC::ARMv7Disassembler::ARMv7DOpcode::ARMv7DOpcode):
(JSC::ARMv7Disassembler::ARMv7DOpcode::is32BitInstruction):
(JSC::ARMv7Disassembler::ARMv7DOpcode::isFPInstruction):
(JSC::ARMv7Disassembler::ARMv7DOpcode::conditionName):
(JSC::ARMv7Disassembler::ARMv7DOpcode::shiftName):
(JSC::ARMv7Disassembler::ARMv7DOpcode::inITBlock):
(JSC::ARMv7Disassembler::ARMv7DOpcode::startingITBlock):
(JSC::ARMv7Disassembler::ARMv7DOpcode::endITBlock):
(JSC::ARMv7Disassembler::ARMv7DOpcode::appendInstructionNameNoITBlock):
(JSC::ARMv7Disassembler::ARMv7DOpcode::appendSeparator):
(JSC::ARMv7Disassembler::ARMv7DOpcode::appendCharacter):
(JSC::ARMv7Disassembler::ARMv7DOpcode::appendString):
(JSC::ARMv7Disassembler::ARMv7DOpcode::appendShiftType):
(JSC::ARMv7Disassembler::ARMv7DOpcode::appendSignedImmediate):
(JSC::ARMv7Disassembler::ARMv7DOpcode::appendUnsignedImmediate):
(JSC::ARMv7Disassembler::ARMv7DOpcode::appendPCRelativeOffset):
(JSC::ARMv7Disassembler::ARMv7DOpcode::appendShiftAmount):
(ARMv7D16BitOpcode):
(OpcodeGroup):
(JSC::ARMv7Disassembler::ARMv7D16BitOpcode::OpcodeGroup::OpcodeGroup):
(JSC::ARMv7Disassembler::ARMv7D16BitOpcode::OpcodeGroup::setNext):
(JSC::ARMv7Disassembler::ARMv7D16BitOpcode::OpcodeGroup::next):
(JSC::ARMv7Disassembler::ARMv7D16BitOpcode::OpcodeGroup::matches):
(JSC::ARMv7Disassembler::ARMv7D16BitOpcode::OpcodeGroup::format):
(JSC::ARMv7Disassembler::ARMv7D16BitOpcode::rm):
(JSC::ARMv7Disassembler::ARMv7D16BitOpcode::rd):
(JSC::ARMv7Disassembler::ARMv7D16BitOpcode::opcodeGroupNumber):
(ARMv7DOpcodeAddRegisterT2):
(JSC::ARMv7Disassembler::ARMv7DOpcodeAddRegisterT2::rdn):
(JSC::ARMv7Disassembler::ARMv7DOpcodeAddRegisterT2::rm):
(ARMv7DOpcodeAddSPPlusImmediate):
(JSC::ARMv7Disassembler::ARMv7DOpcodeAddSPPlusImmediate::rd):
(JSC::ARMv7Disassembler::ARMv7DOpcodeAddSPPlusImmediate::immediate8):
(ARMv7DOpcodeAddSubtract):
(ARMv7DOpcodeAddSubtractT1):
(JSC::ARMv7Disassembler::ARMv7DOpcodeAddSubtractT1::opName):
(JSC::ARMv7Disassembler::ARMv7DOpcodeAddSubtractT1::op):
(JSC::ARMv7Disassembler::ARMv7DOpcodeAddSubtractT1::rm):
(JSC::ARMv7Disassembler::ARMv7DOpcodeAddSubtractT1::rn):
(ARMv7DOpcodeAddSubtractImmediate3):
(JSC::ARMv7Disassembler::ARMv7DOpcodeAddSubtractImmediate3::opName):
(JSC::ARMv7Disassembler::ARMv7DOpcodeAddSubtractImmediate3::op):
(JSC::ARMv7Disassembler::ARMv7DOpcodeAddSubtractImmediate3::immediate3):
(JSC::ARMv7Disassembler::ARMv7DOpcodeAddSubtractImmediate3::rn):
(ARMv7DOpcodeAddSubtractImmediate8):
(JSC::ARMv7Disassembler::ARMv7DOpcodeAddSubtractImmediate8::opName):
(JSC::ARMv7Disassembler::ARMv7DOpcodeAddSubtractImmediate8::op):
(JSC::ARMv7Disassembler::ARMv7DOpcodeAddSubtractImmediate8::rdn):
(JSC::ARMv7Disassembler::ARMv7DOpcodeAddSubtractImmediate8::immediate8):
(ARMv7DOpcodeBranchConditionalT1):
(JSC::ARMv7Disassembler::ARMv7DOpcodeBranchConditionalT1::condition):
(JSC::ARMv7Disassembler::ARMv7DOpcodeBranchConditionalT1::offset):
(ARMv7DOpcodeBranchExchangeT1):
(JSC::ARMv7Disassembler::ARMv7DOpcodeBranchExchangeT1::opName):
(JSC::ARMv7Disassembler::ARMv7DOpcodeBranchExchangeT1::rm):
(ARMv7DOpcodeBranchT2):
(JSC::ARMv7Disassembler::ARMv7DOpcodeBranchT2::immediate11):
(ARMv7DOpcodeCompareImmediateT1):
(JSC::ARMv7Disassembler::ARMv7DOpcodeCompareImmediateT1::rn):
(JSC::ARMv7Disassembler::ARMv7DOpcodeCompareImmediateT1::immediate8):
(ARMv7DOpcodeCompareRegisterT1):
(JSC::ARMv7Disassembler::ARMv7DOpcodeCompareRegisterT1::rn):
(ARMv7DOpcodeCompareRegisterT2):
(JSC::ARMv7Disassembler::ARMv7DOpcodeCompareRegisterT2::rn):
(JSC::ARMv7Disassembler::ARMv7DOpcodeCompareRegisterT2::rm):
(ARMv7DOpcodeDataProcessingRegisterT1):
(JSC::ARMv7Disassembler::ARMv7DOpcodeDataProcessingRegisterT1::opName):
(JSC::ARMv7Disassembler::ARMv7DOpcodeDataProcessingRegisterT1::op):
(JSC::ARMv7Disassembler::ARMv7DOpcodeDataProcessingRegisterT1::rm):
(JSC::ARMv7Disassembler::ARMv7DOpcodeDataProcessingRegisterT1::rdn):
(ARMv7DOpcodeGeneratePCRelativeAddress):
(JSC::ARMv7Disassembler::ARMv7DOpcodeGeneratePCRelativeAddress::rd):
(JSC::ARMv7Disassembler::ARMv7DOpcodeGeneratePCRelativeAddress::immediate8):
(ARMv7DOpcodeLoadFromLiteralPool):
(JSC::ARMv7Disassembler::ARMv7DOpcodeLoadFromLiteralPool::rt):
(JSC::ARMv7Disassembler::ARMv7DOpcodeLoadFromLiteralPool::immediate8):
(ARMv7DOpcodeLoadStoreRegisterImmediate):
(JSC::ARMv7Disassembler::ARMv7DOpcodeLoadStoreRegisterImmediate::opName):
(JSC::ARMv7Disassembler::ARMv7DOpcodeLoadStoreRegisterImmediate::op):
(JSC::ARMv7Disassembler::ARMv7DOpcodeLoadStoreRegisterImmediate::immediate5):
(JSC::ARMv7Disassembler::ARMv7DOpcodeLoadStoreRegisterImmediate::rn):
(JSC::ARMv7Disassembler::ARMv7DOpcodeLoadStoreRegisterImmediate::rt):
(JSC::ARMv7Disassembler::ARMv7DOpcodeLoadStoreRegisterImmediate::scale):
(ARMv7DOpcodeLoadStoreRegisterImmediateWordAndByte):
(ARMv7DOpcodeLoadStoreRegisterImmediateHalfWord):
(ARMv7DOpcodeLoadStoreRegisterOffsetT1):
(JSC::ARMv7Disassembler::ARMv7DOpcodeLoadStoreRegisterOffsetT1::opName):
(JSC::ARMv7Disassembler::ARMv7DOpcodeLoadStoreRegisterOffsetT1::opB):
(JSC::ARMv7Disassembler::ARMv7DOpcodeLoadStoreRegisterOffsetT1::rm):
(JSC::ARMv7Disassembler::ARMv7DOpcodeLoadStoreRegisterOffsetT1::rn):
(JSC::ARMv7Disassembler::ARMv7DOpcodeLoadStoreRegisterOffsetT1::rt):
(ARMv7DOpcodeLoadStoreRegisterSPRelative):
(JSC::ARMv7Disassembler::ARMv7DOpcodeLoadStoreRegisterSPRelative::opName):
(JSC::ARMv7Disassembler::ARMv7DOpcodeLoadStoreRegisterSPRelative::op):
(JSC::ARMv7Disassembler::ARMv7DOpcodeLoadStoreRegisterSPRelative::rt):
(JSC::ARMv7Disassembler::ARMv7DOpcodeLoadStoreRegisterSPRelative::immediate8):
(ARMv7DOpcodeLogicalImmediateT1):
(JSC::ARMv7Disassembler::ARMv7DOpcodeLogicalImmediateT1::opName):
(JSC::ARMv7Disassembler::ARMv7DOpcodeLogicalImmediateT1::op):
(JSC::ARMv7Disassembler::ARMv7DOpcodeLogicalImmediateT1::immediate5):
(ARMv7DOpcodeMiscAddSubSP):
(JSC::ARMv7Disassembler::ARMv7DOpcodeMiscAddSubSP::opName):
(JSC::ARMv7Disassembler::ARMv7DOpcodeMiscAddSubSP::op):
(JSC::ARMv7Disassembler::ARMv7DOpcodeMiscAddSubSP::immediate7):
(ARMv7DOpcodeMiscByteHalfwordOps):
(JSC::ARMv7Disassembler::ARMv7DOpcodeMiscByteHalfwordOps::opName):
(JSC::ARMv7Disassembler::ARMv7DOpcodeMiscByteHalfwordOps::op):
(ARMv7DOpcodeMiscBreakpointT1):
(JSC::ARMv7Disassembler::ARMv7DOpcodeMiscBreakpointT1::immediate8):
(ARMv7DOpcodeMiscCompareAndBranch):
(JSC::ARMv7Disassembler::ARMv7DOpcodeMiscCompareAndBranch::opName):
(JSC::ARMv7Disassembler::ARMv7DOpcodeMiscCompareAndBranch::op):
(JSC::ARMv7Disassembler::ARMv7DOpcodeMiscCompareAndBranch::immediate6):
(JSC::ARMv7Disassembler::ARMv7DOpcodeMiscCompareAndBranch::rn):
(ARMv7DOpcodeMiscHint16):
(JSC::ARMv7Disassembler::ARMv7DOpcodeMiscHint16::opName):
(JSC::ARMv7Disassembler::ARMv7DOpcodeMiscHint16::opA):
(ARMv7DOpcodeMiscIfThenT1):
(JSC::ARMv7Disassembler::ARMv7DOpcodeMiscIfThenT1::firstCondition):
(JSC::ARMv7Disassembler::ARMv7DOpcodeMiscIfThenT1::mask):
(ARMv7DOpcodeMiscPushPop):
(JSC::ARMv7Disassembler::ARMv7DOpcodeMiscPushPop::opName):
(JSC::ARMv7Disassembler::ARMv7DOpcodeMiscPushPop::op):
(JSC::ARMv7Disassembler::ARMv7DOpcodeMiscPushPop::registerMask):
(ARMv7DOpcodeMoveImmediateT1):
(JSC::ARMv7Disassembler::ARMv7DOpcodeMoveImmediateT1::rd):
(JSC::ARMv7Disassembler::ARMv7DOpcodeMoveImmediateT1::immediate8):
(ARMv7DOpcodeMoveRegisterT1):
(JSC::ARMv7Disassembler::ARMv7DOpcodeMoveRegisterT1::rd):
(JSC::ARMv7Disassembler::ARMv7DOpcodeMoveRegisterT1::rm):
(ARMv7D32BitOpcode):
(JSC::ARMv7Disassembler::ARMv7D32BitOpcode::OpcodeGroup::OpcodeGroup):
(JSC::ARMv7Disassembler::ARMv7D32BitOpcode::OpcodeGroup::setNext):
(JSC::ARMv7Disassembler::ARMv7D32BitOpcode::OpcodeGroup::next):
(JSC::ARMv7Disassembler::ARMv7D32BitOpcode::OpcodeGroup::matches):
(JSC::ARMv7Disassembler::ARMv7D32BitOpcode::OpcodeGroup::format):
(JSC::ARMv7Disassembler::ARMv7D32BitOpcode::rd):
(JSC::ARMv7Disassembler::ARMv7D32BitOpcode::rm):
(JSC::ARMv7Disassembler::ARMv7D32BitOpcode::rn):
(JSC::ARMv7Disassembler::ARMv7D32BitOpcode::rt):
(JSC::ARMv7Disassembler::ARMv7D32BitOpcode::opcodeGroupNumber):
(ARMv7DOpcodeBranchRelative):
(JSC::ARMv7Disassembler::ARMv7DOpcodeBranchRelative::sBit):
(JSC::ARMv7Disassembler::ARMv7DOpcodeBranchRelative::j1):
(JSC::ARMv7Disassembler::ARMv7DOpcodeBranchRelative::j2):
(JSC::ARMv7Disassembler::ARMv7DOpcodeBranchRelative::immediate11):
(ARMv7DOpcodeConditionalBranchT3):
(JSC::ARMv7Disassembler::ARMv7DOpcodeConditionalBranchT3::offset):
(JSC::ARMv7Disassembler::ARMv7DOpcodeConditionalBranchT3::condition):
(JSC::ARMv7Disassembler::ARMv7DOpcodeConditionalBranchT3::immediate6):
(ARMv7DOpcodeBranchOrBranchLink):
(JSC::ARMv7Disassembler::ARMv7DOpcodeBranchOrBranchLink::offset):
(JSC::ARMv7Disassembler::ARMv7DOpcodeBranchOrBranchLink::immediate10):
(JSC::ARMv7Disassembler::ARMv7DOpcodeBranchOrBranchLink::isBL):
(ARMv7DOpcodeDataProcessingLogicalAndRithmetic):
(ARMv7DOpcodeDataProcessingModifiedImmediate):
(JSC::ARMv7Disassembler::ARMv7DOpcodeDataProcessingModifiedImmediate::opName):
(JSC::ARMv7Disassembler::ARMv7DOpcodeDataProcessingModifiedImmediate::op):
(JSC::ARMv7Disassembler::ARMv7DOpcodeDataProcessingModifiedImmediate::sBit):
(JSC::ARMv7Disassembler::ARMv7DOpcodeDataProcessingModifiedImmediate::immediate12):
(ARMv7DOpcodeDataProcessingShiftedReg):
(JSC::ARMv7Disassembler::ARMv7DOpcodeDataProcessingShiftedReg::opName):
(JSC::ARMv7Disassembler::ARMv7DOpcodeDataProcessingShiftedReg::sBit):
(JSC::ARMv7Disassembler::ARMv7DOpcodeDataProcessingShiftedReg::op):
(JSC::ARMv7Disassembler::ARMv7DOpcodeDataProcessingShiftedReg::immediate5):
(JSC::ARMv7Disassembler::ARMv7DOpcodeDataProcessingShiftedReg::type):
(JSC::ARMv7Disassembler::ARMv7DOpcodeDataProcessingShiftedReg::tbBit):
(JSC::ARMv7Disassembler::ARMv7DOpcodeDataProcessingShiftedReg::tBit):
(ARMv7DOpcodeDataProcessingReg):
(JSC::ARMv7Disassembler::ARMv7DOpcodeDataProcessingReg::op1):
(JSC::ARMv7Disassembler::ARMv7DOpcodeDataProcessingReg::op2):
(ARMv7DOpcodeDataProcessingRegShift):
(JSC::ARMv7Disassembler::ARMv7DOpcodeDataProcessingRegShift::opName):
(ARMv7DOpcodeDataProcessingRegExtend):
(JSC::ARMv7Disassembler::ARMv7DOpcodeDataProcessingRegExtend::opExtendName):
(JSC::ARMv7Disassembler::ARMv7DOpcodeDataProcessingRegExtend::opExtendAndAddName):
(JSC::ARMv7Disassembler::ARMv7DOpcodeDataProcessingRegExtend::rotate):
(ARMv7DOpcodeDataProcessingRegParallel):
(JSC::ARMv7Disassembler::ARMv7DOpcodeDataProcessingRegParallel::opName):
(ARMv7DOpcodeDataProcessingRegMisc):
(JSC::ARMv7Disassembler::ARMv7DOpcodeDataProcessingRegMisc::opName):
(ARMv7DOpcodeHint32):
(JSC::ARMv7Disassembler::ARMv7DOpcodeHint32::opName):
(JSC::ARMv7Disassembler::ARMv7DOpcodeHint32::isDebugHint):
(JSC::ARMv7Disassembler::ARMv7DOpcodeHint32::debugOption):
(JSC::ARMv7Disassembler::ARMv7DOpcodeHint32::op):
(ARMv7DOpcodeFPTransfer):
(JSC::ARMv7Disassembler::ARMv7DOpcodeFPTransfer::opH):
(JSC::ARMv7Disassembler::ARMv7DOpcodeFPTransfer::opL):
(JSC::ARMv7Disassembler::ARMv7DOpcodeFPTransfer::rt):
(JSC::ARMv7Disassembler::ARMv7DOpcodeFPTransfer::opC):
(JSC::ARMv7Disassembler::ARMv7DOpcodeFPTransfer::opB):
(JSC::ARMv7Disassembler::ARMv7DOpcodeFPTransfer::vd):
(JSC::ARMv7Disassembler::ARMv7DOpcodeFPTransfer::vn):
(ARMv7DOpcodeDataLoad):
(JSC::ARMv7Disassembler::ARMv7DOpcodeDataLoad::opName):
(JSC::ARMv7Disassembler::ARMv7DOpcodeDataLoad::op):
(ARMv7DOpcodeLoadRegister):
(JSC::ARMv7Disassembler::ARMv7DOpcodeLoadRegister::immediate2):
(ARMv7DOpcodeLoadSignedImmediate):
(JSC::ARMv7Disassembler::ARMv7DOpcodeLoadSignedImmediate::pBit):
(JSC::ARMv7Disassembler::ARMv7DOpcodeLoadSignedImmediate::uBit):
(JSC::ARMv7Disassembler::ARMv7DOpcodeLoadSignedImmediate::wBit):
(JSC::ARMv7Disassembler::ARMv7DOpcodeLoadSignedImmediate::immediate8):
(ARMv7DOpcodeLoadUnsignedImmediate):
(JSC::ARMv7Disassembler::ARMv7DOpcodeLoadUnsignedImmediate::immediate12):
(ARMv7DOpcodeLongMultipleDivide):
(JSC::ARMv7Disassembler::ARMv7DOpcodeLongMultipleDivide::opName):
(JSC::ARMv7Disassembler::ARMv7DOpcodeLongMultipleDivide::smlalOpName):
(JSC::ARMv7Disassembler::ARMv7DOpcodeLongMultipleDivide::smlaldOpName):
(JSC::ARMv7Disassembler::ARMv7DOpcodeLongMultipleDivide::smlsldOpName):
(JSC::ARMv7Disassembler::ARMv7DOpcodeLongMultipleDivide::rdLo):
(JSC::ARMv7Disassembler::ARMv7DOpcodeLongMultipleDivide::rdHi):
(JSC::ARMv7Disassembler::ARMv7DOpcodeLongMultipleDivide::op1):
(JSC::ARMv7Disassembler::ARMv7DOpcodeLongMultipleDivide::op2):
(JSC::ARMv7Disassembler::ARMv7DOpcodeLongMultipleDivide::nBit):
(JSC::ARMv7Disassembler::ARMv7DOpcodeLongMultipleDivide::mBit):
(ARMv7DOpcodeDataPushPopSingle):
(JSC::ARMv7Disassembler::ARMv7DOpcodeDataPushPopSingle::opName):
(JSC::ARMv7Disassembler::ARMv7DOpcodeDataPushPopSingle::op):
(ARMv7DOpcodeDataStoreSingle):
(JSC::ARMv7Disassembler::ARMv7DOpcodeDataStoreSingle::opName):
(JSC::ARMv7Disassembler::ARMv7DOpcodeDataStoreSingle::op):
(ARMv7DOpcodeStoreSingleImmediate12):
(JSC::ARMv7Disassembler::ARMv7DOpcodeStoreSingleImmediate12::immediate12):
(ARMv7DOpcodeStoreSingleImmediate8):
(JSC::ARMv7Disassembler::ARMv7DOpcodeStoreSingleImmediate8::pBit):
(JSC::ARMv7Disassembler::ARMv7DOpcodeStoreSingleImmediate8::uBit):
(JSC::ARMv7Disassembler::ARMv7DOpcodeStoreSingleImmediate8::wBit):
(JSC::ARMv7Disassembler::ARMv7DOpcodeStoreSingleImmediate8::immediate8):
(ARMv7DOpcodeStoreSingleRegister):
(JSC::ARMv7Disassembler::ARMv7DOpcodeStoreSingleRegister::immediate2):
(ARMv7DOpcodeUnmodifiedImmediate):
(JSC::ARMv7Disassembler::ARMv7DOpcodeUnmodifiedImmediate::opName):
(JSC::ARMv7Disassembler::ARMv7DOpcodeUnmodifiedImmediate::op):
(JSC::ARMv7Disassembler::ARMv7DOpcodeUnmodifiedImmediate::shBit):
(JSC::ARMv7Disassembler::ARMv7DOpcodeUnmodifiedImmediate::bitNumOrSatImmediate):
(JSC::ARMv7Disassembler::ARMv7DOpcodeUnmodifiedImmediate::immediate5):
(JSC::ARMv7Disassembler::ARMv7DOpcodeUnmodifiedImmediate::immediate12):
(JSC::ARMv7Disassembler::ARMv7DOpcodeUnmodifiedImmediate::immediate16):
(ARMv7DOpcodeVMOVDoublePrecision):
(JSC::ARMv7Disassembler::ARMv7DOpcodeVMOVDoublePrecision::op):
(JSC::ARMv7Disassembler::ARMv7DOpcodeVMOVDoublePrecision::rt2):
(JSC::ARMv7Disassembler::ARMv7DOpcodeVMOVDoublePrecision::rt):
(JSC::ARMv7Disassembler::ARMv7DOpcodeVMOVDoublePrecision::vm):
(ARMv7DOpcodeVMOVSinglePrecision):
(JSC::ARMv7Disassembler::ARMv7DOpcodeVMOVSinglePrecision::op):
(JSC::ARMv7Disassembler::ARMv7DOpcodeVMOVSinglePrecision::rt2):
(JSC::ARMv7Disassembler::ARMv7DOpcodeVMOVSinglePrecision::rt):
(JSC::ARMv7Disassembler::ARMv7DOpcodeVMOVSinglePrecision::vm):
(ARMv7DOpcodeVMSR):
(JSC::ARMv7Disassembler::ARMv7DOpcodeVMSR::opL):
(JSC::ARMv7Disassembler::ARMv7DOpcodeVMSR::rt):
* disassembler/ARMv7Disassembler.cpp: Added.
(JSC::tryToDisassemble):

Source/WTF: 

Added a new disassembler for ARMv7 Thumb2 instructions for use by the JSC debugging
and profiling code.  Enabled the disassembler for IOS bulds.

* wtf/Platform.h:


git-svn-id: http://svn.webkit.org/repository/webkit/trunk@149821 268f45cc-cd09-0410-ab3c-d52691b4dbfc
    ac9f0e52